Semiconductor device having a contact window and fabrication method thereof

ABSTRACT

Semiconductor devices having a contact window and fabrication methods thereof are provided. A lower dielectric layer, conductive patterns and an upper dielectric layer are formed sequentially on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than that of the upper dielectric layer. The upper dielectric layer and the lower dielectric layer are patterned by anisotropic etching to form a trench without exposing the semiconductor substrate. The resultant structure is subject to isotropic etching to expose the substrate and to form a contact window having a wider width in a lower region than in an upper region without damaging the semiconductor substrate.

[0001] This application relies for priority upon Korean PatentApplication No. 2000-64054, filed on Oct. 30, 2000, the contents ofwhich are herein incorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to semiconductor devices andfabrication methods thereof and, more particularly, to semiconductordevices having a contact window providing low contact resistance andhigh reliability and fabrication methods thereof.

[0004] 2. Description of the Related Art

[0005] Multilevel interconnection in a semiconductor device is importantfor achieving higher device density and performance. Especially,structures of contact windows and fabrication method for forming thecontact windows are essential for forming the multilevelinterconnection. The contact windows electrically connect a wiring layerto a semiconductor substrate or connect a wiring layer to another wiringlayer. With increased device density, a depth of the contact windowtends to be deeper and its width tends to be narrower. The narrow widthof the contact window leads to problems such as a small contact areaand, as a result, high contact resistance.

[0006] With increased device density, a space between conductivepatterns also tends to be closer and closer. This tendency makes thewidth of the contact window more decreased. This is because the contactwindow is generally formed to pass through a dielectric material betweenthe conductive patterns. This will be further described below withreference to drawings.

[0007] FIGS. 1 to 4 are cross sectional views illustrating a process forforming a contact window in a semiconductor device in accordance with aKorean Patent Laid-open Publication No.99-46930.

[0008] Referring to FIGS. 1 and 2, a lower dielectric layer 5,conductive patterns 7 and an upper dielectric layer 9 are formed insequence on a semiconductor substrate 1 having an impurity active region3. The impurity active region 3 has a predetermined width 13. The lowerdielectric layer 5 has a higher wet etch rate than a wet etch rate ofthe upper dielectric layer 9 for a selected oxide etching solution suchas hydrofluoric acid (HF) solution. The lower dielectric layer 5 isformed of a borophosphosilicate glass (BPSG) layer or a spin-on-glass(SOG) layer. The upper dielectric layer 9 is formed of an undopedsilicate glass (USG) layer or a high density plasma (HDP) oxide layer.On the upper dielectric layer 9, a photoresist pattern 11 having anopening is formed to define a contact window area. The upper dielectriclayer 9 and the lower dielectric layer 5 are partially removed by a dryetching process using the photoresist pattern 11 as an etch mask. As aresult, a contact window 19 is formed to expose the impurity activeregion 3. At this time, the conductive patterns 7 should not be exposedby the contact window 19 as shown in FIG. 2. Therefore, the width 21 ofthe contact window 19 should be narrower than the spacing 15 between theconductive patterns 7.

[0009] The exposed surface 22 of the impurity active region 3 isseverely damaged due to the dry etching process during formation of thecontact window 19. Accordingly, the etching damage may increase contactresistance and junction leakage current.

[0010] Referring to FIG. 3, the resultant structure is dipped into theselected oxide etching solution to form a final contact window 19′. Withthis wet etching, the upper dielectric layer 9 is etched to a lesserextent of a selected width 20 in a lateral direction; the lowerdielectric layer 5 is etched to greater extent in the lateral direction.Consequently, the final contact window 19′ has a wider width 21′ in alower region than the width in an upper region. Therefore, an exposedsurface area of the impurity active region 3 is increased by the wetetching, as compared with an exposed surface area formed immediatelyafter the dry etching. Referring to FIG. 4, the photoresist pattern 11is removed. Then, a wiring material 24 is formed on the resultantstructure to fill the contact window 19′.

[0011] In the prior art, the dry etching exposes the semiconductorsubstrate 1. If the dry etching is overdone, it may cause a surfacedamage 22 (See FIG. 2) of the impurity active region 3. Therefore, thedry etching should be controlled with high accuracy to prevent thedamage. This dry etching damage causes serious problems such as highcontact resistance and high junction leakage current in a semiconductordevice.

[0012] The contact window 19 should not expose the conductive patterns 7to insure electrical isolation therebetween. Therefore, a width 17 ofthe opening of the photoresist pattern 11 and a width 21 of the contactwindow 19 should not be increased greater than a distance 15 between theconductive patterns 7. In other words, the shorter the spacing betweenthe conductive patterns 7 is, the narrower the width of the contactwindow 19 is, as described above.

[0013] The wet etching also should be controlled with high accuracy,because a distance 26 between the wiring material 24 and the conductivepatterns 7 needs to be properly maintained. Assume that the wet etchingis overdone and the lower dielectric layer 5 is excessively etched inthe lateral direction, and, as a result, the contact window 19′ exposesa bottom side of the conductive patterns 7. This can result in anundesirable electrical connection between the wiring material 24 and theconductive patterns 7. Therefore, in the prior art, the width 21′ in alower region of the final contact window 19′ cannot be greater than thespacing between the conductive patterns 7. Thus, a contact area betweenthe wiring layer and the conductive patterns 7 is limited by the spacingbetween the conductive patterns 7. Accordingly, it is difficult toreduce contact resistance.

[0014] According to the prior art, the dry and the wet etching should beperformed very carefully. That is to say, it is very difficult tomaintain the high accuracy necessary to avoid above-mentioned problemsduring the dry and wet etching.

SUMMARY OF THE INVENTION

[0015] It is, therefore, an object of the present invention to provide amethod for forming a contact window without dry etching damage in asemiconductor substrate. Another object of the present invention is toprovide a method for forming a contact window that maximizes a contactarea and improves electrical isolation characteristic with neighboringconductive patterns simultaneously.

[0016] Another object of the present invention is to provide a structurefor a contact window that improves the contact resistance and junctionleakage current characteristics as well as the electrical isolationcharacteristic with neighboring conductive patterns.

[0017] According to one aspect of the invention, a method of forming acontact window is provided. This method comprises forming a lowerdielectric layer and an upper dielectric layer in sequence on asemiconductor substrate. The lower dielectric layer has a higherisotropic etch rate than an isotropic etch rate of the upper dielectriclayer for a selected isotropic etching condition. The upper dielectriclayer and the lower dielectric layer are etched by an anisotropicetching to form a trench not exposing the semiconductor substrate.

[0018] Thus, it is possible to prevent the semiconductor substrate frombeing damaged by the anisotropic etching. A sidewall of the trench issubstantially perpendicular to the substrate. The resultant structure issubject to a wet etching using the selected isotropic etching conditionto expose the substrate. A difference in the etch rates of the upper andthe lower dielectric layers makes a contact window having a wider widthin a lower region than a width in a upper region. For example, the lowerdielectric layer is a layer selected from the group consisting of aborophosphosilicate glass (BPSG) layer, a spin-on-glass (SOG) layer andO₃-TEOS layer. The upper dielectric layer is a layer selected from thegroup consisting of an undoped silicate glass (USG) layer, a highdensity plasma (HDP) oxide layer and O₂-TEOS layer. The lower dielectriclayer may be a TEOS layer. The TEOS layer is formed by a process inwhich a flow rate of O₃ gas is decreased and a flow rate of O₂ gas isincreased from an initial stage to an ending stage of the process. Inaddition, before the wet etching, a polymer with a thickness of 100-500Å or a spacer formed of a material selected from the group consisting ofpolycrystalline silicon, silicon nitride and silicon oxynitride may beformed on the sidewall of the trench.

[0019] According to another aspect of the present invention, asemiconductor device is provided. The semiconductor device comprises alower dielectric layer and an upper dielectric layer formed on asubstrate, and a contact window formed through the dielectric layers.The contact window includes an upper contact window and a lower contactwindow extended from the upper contact window to the substrate. Theupper contact window has a sidewall substantially perpendicular to thesubstrate. However, the lower contact window has a sloped sidewallprofile such that a width of the lower contact window becomes wider andwider along the downward direction. The lower dielectric layer is a TEOSlayer. The TEOS layer is formed by a process in which a flow rate of O₃gas is decreased and a flow rate of O₂ gas is increased from an initialstage to an ending stage of the process. The semiconductor device alsohas a plurality of conductive patterns intervening between the upperdielectric layer and the lower dielectric layer. The plurality ofconductive patterns is spaced apart from the contact window. Abottommost width of the contact window may be wider than a space betweenone conductive pattern and the other conductive pattern.

[0020] According to another aspect of the present invention, asemiconductor device has a first dielectric layer, a second dielectriclayer and an upper dielectric layer sequentially stacked on a substrate,and has a contact window penetrating the dielectric layers. Thesemiconductor device also has a plurality of conductive patternsintervening between the first dielectric layer and the second dielectriclayer. The plurality of conductive patterns is spaced apart from thecontact window. The contact window in the first dielectric layer iswider than that in the second dielectric layer and the upper dielectriclayer. A bottommost width of the contact window may be wider than aspace between one conductive pattern and the other conductive pattern.

[0021] Accordingly, it is possible to maximize a contact area between aconductive material filling the contact window and the substrate,resulting in a reduction of the contact resistance. In addition, thesemiconductor device may further comprise a spacer on the sidewall ofthe upper contact window. The spacer is formed of a material selectedfrom the group consisting of polycrystalline silicon, silicon nitrideand silicon oxynitride.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Other features of the present invention will be more readilyunderstood from the following detailed description of specificembodiments when read in conjunction with the accompanying drawings, inwhich:

[0023] FIGS. 1 to 4 are cross-sectional views illustrating aconventional process for forming a contact window in a semiconductordevice.

[0024]FIGS. 5 and 6 are cross-sectional views illustrating a process forforming a contact window in a semiconductor device according to a firstembodiment of the present invention;

[0025]FIGS. 7 and 8 are cross-sectional views illustrating a process forforming a contact window in a semiconductor device according to a secondembodiment of the present invention;

[0026]FIGS. 9 and 10 are cross-sectional views illustrating a processfor forming a contact window in a semiconductor device according to athird embodiment of the present invention;

[0027] FIGS. 11 to 14 are cross-sectional views illustrating a processfor forming a contact window in a semiconductor device according to afourth embodiment of the present invention; and

[0028] FIGS. 15 to 19 are cross-sectional views illustrating a processfor forming a contact window in a semiconductor device according to afifth embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0029] Now, the present invention will be described more fullyhereinafter with reference to the accompanying drawings.

[0030]FIGS. 5 and 6 are cross-sectional views illustrating a process forforming a contact window in a semiconductor device according to a firstembodiment of the present invention.

[0031] Referring to FIG. 5, a lower dielectric layer 105 is formed on asemiconductor substrate 101 having an impurity active region 103. Theimpurity active region 103 is formed by ion implantation. Thesemiconductor substrate 101 may have other types of conductive regionsformed on the substrate. For example, there may be a polycrystallinesilicon pattern, an aluminum wiring pattern or a tungsten plug, or otherconductive regions, instead of the impurity active region 103. The lowerdielectric layer 105 is a borophosphosilicate glass (BPSG) layer formedby chemical vapor deposition (CVD). A desirable thickness of the lowerdielectric layer 105 is within a range of approximately 1000-6000 Å. Inthis embodiment, the lower dielectric layer 105 has a thickness ofapproximately 4000 Å. The lower dielectric layer 105 may be aspin-on-glass (SOG) layer or an O₃-TEOS layer. The O₃-TEOS layer isformed by CVD using TEOS (tetraethylorthosilicate) and O₃. The methodfor forming the O₃-TEOS layer is described in detail in U.S. Pat. No.5,849,635 to Salman Akram et al.

[0032] A conductive layer can be formed to a thickness of approximately500-3000 Å on the surface of the lower dielectric layer 105 by CVD. Theconductive layer can be a doped polycrystalline silicon layer. With thisembodiment, the conductive layer is preferably formed to a thickness ofapproximately 1500 Å. The conductive layer is patterned to formconductive patterns 107 as a local interconnection in the semiconductordevice.

[0033] An upper dielectric layer 109 formed of undoped silicate glass(USG) is deposited on the resultant structure by CVD. A desirablethickness of the upper dielectric layer is within a range ofapproximately 1000-6000 Å. Preferably, the upper dielectric layer 109 isformed to a thickness of approximately 4000 Å. The upper dielectriclayer 109 may be a high-density plasma (HDP) oxide layer or an O₂-TEOSlayer. The O₂-TEOS layer is formed by CVD using TEOS(tetraethylorthosilicate) and O₂. The method for forming the O₂-TEOSlayer is described in detail in the aforementioned U.S. Pat. No.5,849,635. It is well known that wet etch rates of the BPSG layer, theSOG layer and the O₃-TEOS layer are faster than those of the USG layer,the HDP oxide layer and the O₂-TEOS layer for a hydrofluoric acid (HF)solution.

[0034] A photoresist pattern 111 having an opening is formed on theupper dielectric layer 109 using conventional techniques. Thephotoresist pattern 111 exposes a portion of the upper dielectric layer109. The photoresist pattern 111 will be used as an etch mask in anetching process to be described below.

[0035] The upper dielectric layer 109 and lower dielectric layer 105 areetched by a dry etching technique using the photoresist pattern 111 asan etch mask to form a trench 119 having a width 121. Unlike the priorart, the trench does not expose the substrate 101. That is, the dryetching removes only approximately 20-95% of the total thickness of thelower dielectric layer 105, and a remainder 128 of the lower dielectriclayer 105 remains under the trench 119. Therefore, no damage occurs tothe substrate. It is preferable that the dry etching removes onlyapproximately 70-95% of the total thickness of the lower dielectriclayer 105. This is because the thin remainder 128 of the lowerdielectric layer 105 can reduce the rounded sidewall profile of acontact window in the lower dielectric layer 105. (See FIG. 6) In asubsequent process, the rounded profile results from the wet etchingprocess to be described below. In a conventional dry etching technique,the lateral etch rate is considerably lower than the vertical etch rate.Therefore, a sidewall of the trench 119 is perpendicular to thesubstrate 101. But, it is known that, with a specific dry etchingcondition, the sidewall of trench 119 may be angled from substrate 101so that the width of the trench 119 decreases in a direction from anupper region of the trench 119 to a lower region of the trench 119.

[0036] Referring to FIG. 6, an isotropic HF etching solution verticallyremoves the remainder 128 and laterally removes the sidewall of thetrench concurrently. As a result, a contact window 119′ is formed toexpose the impurity active region 103. Through this wet etching, whilethe upper dielectric layer 109 is etched to a lesser extent of aselected width 120 in the lateral direction, the lower dielectric layer105 is etched to a greater extent in the lateral direction.Consequently, the final contact window 119′ has a width 121′ in a lowerregion that is wider than any width located in a region above it, i.e. awidth in an upper region.

[0037] Though not shown in the drawings, the photoresist pattern iscontinuously removed and then a wiring material is formed on the upperdielectric layer 109 and inside the contact window 119′.

[0038] As described in the first embodiment, because the dry etchingdoes not expose the substrate, damage to the impurity active region canbe prevented. Therefore, it is possible to realize a reliablesemiconductor device having a low contact resistance.

[0039]FIGS. 7 and 8 are cross sectional views illustrating a process forforming a contact window in a semiconductor device according to a secondembodiment of a present invention.

[0040] Referring to FIG. 7, a first dielectric layer 205 a is formed ona semiconductor substrate 201 having an impurity active region 203. Theimpurity active region 103 is formed by ion implantation. The firstdielectric layer 205 a is a BPSG layer formed by CVD. A desirablethickness of the first dielectric layer 205 a is within a range of 500Å-3000 Å. In this embodiment, the first dielectric layer 205 a has athickness of approximately 2000 Å. The first dielectric layer 205 a maybe an SOG layer or an O₃-TEOS layer.

[0041] A second dielectric layer 205 b is formed on the first dielectriclayer 205 a. The second dielectric layer 205 b is a USG layer made byCVD. A desirable thickness of the second dielectric layer is within arange of 500-3000 Å. In this embodiment, the second dielectric layer 205b has a thickness of approximately 2000 Å. The second dielectric layer205 b may be an HDP oxide layer or an O₂-TEOS layer. A lower dielectriclayer 205 comprises the first dielectric layer 205 a and the seconddielectric layer 205 b. Preferably, the first dielectric layer 205 acomprises a material having a higher isotropic etch rate than that ofthe second dielectric layer 205 b.

[0042] On the second dielectric layer 205 b, a conductive layer isformed by CVD to a desirable thickness of approximately 500-3000 Å. Anexample of the conductive layer is a doped polycrystalline siliconlayer. In this embodiment, the conductive layer has a thickness ofapproximately 1500 Å. The conductive layer is patterned to formconductive patterns 207 that are used as local interconnections in thesemiconductor device.

[0043] On the conductive patterns 207 and the second dielectric layer205 b, an upper dielectric layer 209 of USG is formed. A desirablethickness of the upper dielectric layer 209 is within a range ofapproximately 1000-6000 Å. In this embodiment, the upper dielectriclayer 209 has a thickness of approximately 4000 Å. The upper dielectriclayer 209 may be an HDP oxide layer or an O₂-TEOS layer.

[0044] A photoresist pattern 211 is formed on the upper dielectric layer209 using conventional techniques. The photoresist pattern 211 exposes aportion of the upper dielectric layer 209.

[0045] The upper dielectric layer 209 and second dielectric layer 205 bare anisotropically etched, e.g., dry etched using the photoresistpattern 211 as an etching mask to form a trench 219 having a width 221.Unlike the prior art, this dry etching does not expose the substrate201. That is, the first dielectric layer 205 a remains under trench 219.Therefore, no damage to the semiconductor substrate 201 occurs.

[0046] In this embodiment, the bottom of the trench 219, that is, an endpoint of the dry etching, is located at a boundary between the firstdielectric layer 205 a and second dielectric layer 205 b. But a portionof the first dielectric layer 205 a may be removed and the bottom of thetrench may be located in the first dielectric layer 205 a. In this case,the dry etching removes approximately 20-95% of the total thickness ofthe first dielectric layer 205 a. More preferably the dry etchingremoves approximately 70-95% of the total thickness of the firstdielectric layer 205 a. This is because the smaller remainder of thefirst dielectric layer 205 a is more easily reduced to a rounded profilefor a contact window in a region adjacent to the substrate. (See FIG. 8)The rounded profile results from a wet etching process to be describedbelow.

[0047] Referring to FIG. 8, the dielectric material remaining under thetrench is removed while lateral etching is simultaneously performed byan isotropic etching process using an HF solution. As a result, acontact window 219′ is formed to expose the impurity active region 203.Through this wet etching, while the upper dielectric layer 209 and thesecond dielectric layer 205 b are etched to a lesser extent in a lateraldirection, the first dielectric layer 205 a is etched to a greaterextent in the lateral direction. Consequently, the final contact window219′ has a width 221′ in a lower region greater than the width in anupper region of the window 219′.

[0048] Furthermore, even if the wet etching process is performedexcessively, it can prevent the conductive patterns 207 from beingexposed by contact window 219′. This is due to the presence of thesecond dielectric layer 205 b having a lower isotropic etch rate, underthe conductive pattern 207. Accordingly, it is possible to keep apredetermined distance 220 between the conductive patterns 207 and thecontact window 219′.

[0049] Subsequently, though not shown in the drawings, the photoresistpattern 211 is removed and a wiring material is formed on the upperdielectric layer 209 and inside the contact window 219′.

[0050] As described in the second embodiment, because the dry etchingdoes not expose the substrate 201, the damage to the impurity activeregion can be prevented. Moreover, the spacing between the contactwindow and the conductive patterns can be sufficiently maintained.Therefore, the wet etching can be performed to the extent necessary tomaximize the lateral etching in the first dielectric layer. This meansthat the width 221′ can be larger than the spacing between theconductive patterns 207. Thus, it is possible to maximize the exposedarea of the impurity active region 203 without exposing the conductivepatterns 207 and improve the contact resistance.

[0051]FIGS. 9 and 10 are cross sectional views illustrating a processfor forming a contact window in a semiconductor device according to athird embodiment of the present invention.

[0052] Referring to FIG. 9, a lower dielectric layer 305 is formed on asemiconductor substrate 301 having an impurity active region 303. Theimpurity active region 303 is formed by ion implantation. The lowerdielectric layer 305 is a TEOS layer formed by CVD using TEOS, O₃ andO₂. The TEOS layer is formed by a process in which a flow rate of O₃ gasdecreases and a flow rate of O₂ gas increases from an initial stage toan ending stage of the process. The TEOS layer has an etch rate thatgradually decreases in a direction from its bottom to the top, i.e. anetch rate that increases in a direction toward the substrate 301. Adesirable thickness of the lower dielectric layer 305 is within a rangeof approximately 1000-6000 Å. In this embodiment, the lower dielectriclayer 305 has a thickness of approximately 4000 Å. It is preferable thatan upper region of the TEOS layer has a thickness of approximately500-1000 Å and has the same etch rate as that of an upper dielectriclayer 309 to be formed later. A method for forming the TEOS layer isalso described in detail in U.S. Pat. No. 5,849,635 issued to SalmanAkram et al.

[0053] On the lower dielectric layer 305, conductive patterns 307 can beformed in the same manner as described in the first and secondembodiments of the present invention with reference to FIGS. 5 to 8.

[0054] On the resultant structure having the conductive patterns 307, anupper dielectric layer 309 of USG is formed using CVD. A desirablethickness of the upper dielectric layer is within a range of 1000-6000Å. In this embodiment, the upper dielectric layer 309 has a thickness ofapproximately 4000 Å. The upper dielectric layer 309 may be an HDP oxidelayer or an O₂-TEOS layer.

[0055] A photoresist pattern 311 is formed on the upper dielectric layer309 by a well-known photolithographic and etching processes. Thephotoresist pattern 311 exposes a portion of the upper dielectric layer309.

[0056] The upper dielectric layer 309 and lower dielectric layer 305 areetched by a dry etching technique using the photoresist pattern 311 as aetching mask to form a trench 319 having a width 321. Unlike the priorart, this dry etching does not expose the substrate 301. That is, thedry etching removes approximately 20-95% of the total thickness of thelower dielectric layer 305. It is preferable that the dry etchingremoves approximately 70-95% of the total thickness of the lowerdielectric layer 305.

[0057] Referring to FIG. 10, an isotropic etching process using an HFsolution forms a contact window 319′ exposing the impurity active region303. Through this wet etching, the upper dielectric layer 309 is etchedto a lesser extent in a lateral direction while, the lower dielectriclayer 305 is etched to a greater extent in the lateral directionresulting in a sidewall profile having a negative slope. Consequently,the final contact window 319′ has a width 321′ in a lower region greaterthan a width in an upper region. In other words, the width of contactwindow 319′ increases as one moves toward the substrate.

[0058] Subsequently, though not shown in the drawings, the photoresistpattern 311 is removed and a wiring material is formed on the upperdielectric layer 309 and inside the contact window 319′.

[0059] As described in the third embodiment, because the dry etchingdoes not expose the substrate 301, the damage to the impurity activeregion 303 is substantially prevented. In addition, the distance (320 ofFIG. 10) between the contact window and the conductive patterns can bemaintained with sufficient thickness. This is because the etch rate ofthe lower dielectric layer 305 gradually decreases in the direction frombottom to top, and the etch rate in the upper region of the lowerdielectric layer 305 is relatively low. Moreover, a width of thebottommost region of the contact window 319′ can be made larger than thespacing between the conductive patterns 307. This is because the etchrate in the bottommost region of the lower dielectric layer can be setrelatively high.

[0060]FIGS. 11 and 12 are cross sectional views illustrating a processfor forming a contact window in a semiconductor device according to afourth embodiment of the present invention.

[0061] Referring to FIG. 11, a lower dielectric layer 405 is formed on asemiconductor substrate 401 having an impurity active region 403. Theimpurity active region 403 is formed by ion implantation. The lowerdielectric layer 405 is a TEOS layer as described in the thirdembodiment of the present invention. Also, conductive patterns 407, anupper dielectric layer 409, and a photoresist pattern 411 are formed bythe same method as the third embodiment of the present invention.

[0062] The upper dielectric layer 409 and the lower dielectric layer 405are etched by a dry etching technique using the photoresist pattern 411as an etching mask to form a trench 419. Unlike the prior art, this dryetching does not expose the substrate 401. That is, the remainder of thelower dielectric layer 405 exists under the trench 419 with a thicknessof approximately 500-3000 Å. In this embodiment, the remainder has athickness of approximately 2000 Å. Meanwhile, the dry etching iscontrolled in order to form a polymer layer 432 on the sidewall of thephotoresist pattern 411 and the trench 419. The polymer layer 432 shouldbe thick enough to suppress a lateral anisotropic etching to beperformed in a subsequent process. In this embodiment, it is preferablethat the polymer layer 432 has a thickness of 100-500 Å.

[0063] It is well known that carbon-oxygen gas enhances generation of apolymer on a sidewall of an etched region. The carbon-oxygen gasenhances the formation of free carbon species that react with otherspecies such as nitrogen, fluorine or boron, thereby forming polymer.This polymer is deposited on the sidewalls of the etched region.Therefore, in a dry etching process, increasing the flow rate of thecarbon-oxygen gas can enhance generation of the polymer. Suitablecarbon-oxygen gases include for example, CO, HCOOH, or HCHO, of which COis preferred. This method to enhance the formation of polymers has beenwidely used in industry to deposit the polymers on the sidewalls ofetched features during dry etchings. An example of this is described ingreat detail in U.S. Pat. No. 5,843,847 issued to Bryan Pu et al.

[0064] Referring to FIG. 12, an isotropic wet etching process isperformed to remove the remainder of the lower dielectric layer 405 andto perform lateral etching. As a result, a contact window 419′ is formedto expose the impurity active region 403. In this wet etching, thepolymer 432 suppresses the lateral etching on the sidewall of the trench419. Consequently, the lateral etching of the sidewall of trench 419 canbe minimized. Thus, it is possible to keep a predetermined distance 420between the conductive patterns 407 and the contact window 419′. The wetetchant used is a mixture of a deionic (DI) water, NH₄F and HF. A volumepercentage of the HF in the mixture is approximately 0.1-0.4%. Forexample, in this embodiment, the mixture comprises approximately 82.6Vol % DI water, 17.1 Vol % NH₄F, 0.3 Vol % HF.

[0065] Though not shown in the drawings, the photoresist pattern and thepolymer are removed, and a wiring material is formed on the upperdielectric layer 409 and inside the contact window 419′.

[0066]FIGS. 13 and 14 are cross sectional views illustrating slightvariations of the fourth embodiment. The variations are the same as thefourth embodiment except for the differences described below.

[0067] Referring FIG. 13, a lower dielectric layer 405′ comprises afirst dielectric layer 405 a and a second dielectric layer 405 b asdescribed in the second embodiment. That is, the first dielectric layer405 a comprises a BPSG layer, an SOG layer or an O₃-TEOS layer. Thesecond dielectric layer 405 b is formed on the first dielectric layer405 a. The second dielectric layer 205 b comprises a USG layer, an HDPlayer or an O₂-TEOS layer. In FIG. 13, the bottom of the trench 419, anend point of the dry etching, is located at a boundary between the firstdielectric layer 405 a and the second dielectric layer 405 b. However, aportion of the first dielectric layer 405 a may be removed and thebottom of the trench may be located in the first dielectric layer.

[0068] Referring to FIG. 14, a lower dielectric layer 405″ comprises aBPSG layer, an SOG layer or an O₃-TEOS layer as described in the firstembodiment.

[0069] As described in the fourth embodiment and its variations, becausethe dry etching does not expose the substrate, damage to the impurityactive region 403 can be prevented. Moreover, the spacing between thecontact window and the conductive patterns 407 can be maintainedsufficiently thick, since the polymer suppresses the lateral etching onthe sidewall of the trench 419.

[0070] FIGS. 15 to 17 are cross-sectional views illustrating a processfor forming a contact window in a semiconductor device according to afifth embodiment of the present invention.

[0071] Referring to FIG. 15, a lower dielectric layer 505, conductivepatterns 507, and an upper dielectric layer 509 are formed on asemiconductor substrate 501 having an impurity active region 503 usingthe same manner as the third embodiment. On the upper dielectric layer509, a capping layer 510 is formed of polycrystalline silicon, siliconnitride or silicon oxynitride. In this embodiment, the capping layer 510is formed of silicon nitride by CVD.

[0072] A photoresist pattern 511 is formed on the capping layer 510. Thephotoresist pattern 511 exposes a portion of the capping layer 510.

[0073] The capping layer 510, the upper dielectric layer 509 and thelower dielectric layer 505 are etched by a dry etching process using thephotoresist pattern 511 as an etching mask to form a trench 519. Unlikethe prior art, this dry etching does not expose the substrate 501. Thatis, a remainder of the lower dielectric layer exists under the trench519 with a thickness of 500-3000 Å. In this embodiment, the remainderhas a thickness of approximately 2000 Å.

[0074] Referring to FIG. 16, the photoresist pattern 511 is removed,then a spacer 534 is formed on the sidewall of the trench 519 and thecapping layer 510. The spacer 534 can be formed of polycrystallinesilicon. That is, once the resultant structure in which the photoresistpattern 511 is removed, a conformal polycrystalline silicon layer isformed. Then, the conformal polycrystalline silicon layer is etchedanisotropically to form the spacer 534 on the sidewall of the trench 519and the capping layer 510. The spacer 534 may be formed of siliconnitride or silicon oxynitride. In this case, the spacer 534 formed ofsilicon nitride or silicon oxynitride may play a role of one ofdielectric materials between conductive patterns 507 and a wiring layerto be formed later.

[0075] Referring to FIG. 17, an isotropic etching with a wet etchant isperformed to remove the remainder of the lower dielectric layer and toperform lateral etching. As a result, a contact window 519′ is formed toexpose the impurity active region 503. In this wet etching, the spacer534 and the capping layer 510 suppress the wet etching on the sidewallof the trench and an upper surface of the upper dielectric layer tominimize the amount of lateral etching on the sidewall. The wet etchantis a dilute HF solution.

[0076] Though not shown in the drawings, a wiring material is formed onthe upper dielectric layer 509 and inside the contact window 519′.

[0077]FIGS. 18 and 19 are cross sectional views illustrating a sixth andseventh embodiment of the present invention. These embodiments are thesame as the fifth embodiment except for the slight differences describedbelow.

[0078] Referring to FIG. 18, a lower dielectric layer 505′ comprises afirst dielectric layer 505 a and a second dielectric layer 505 b, asdescribed in the second embodiment. That is, the first dielectric layer505 a is one of a BPSG layer, an SOG layer and an O₃-TEOS layer. Thesecond dielectric layer 505 b is formed on the first dielectric layer505 a. The second dielectric layer 505 b is one of a USG layer, an HDPlayer and an O₂-TEOS layer. In FIG. 18, a bottom of the trench 519,e.g., an end point of the dry etching, is located at a boundary betweenthe first dielectric layer 505 a and second dielectric layer 505 b. Aportion of the first dielectric layer 505 a may be removed and thebottom of the trench may be located in the first dielectric layer.

[0079] Referring FIG. 19, a lower dielectric layer 505″ is one of a BPSGlayer, an SOG layer and an O₃-TEOS layer as described in the firstembodiment.

[0080] As described in the fifth embodiment and its variations, becausethe dry etching does not expose the substrate, damage to the impurityactive region can be prevented. Moreover, the space between the contactwindow and the conductive patterns can be sufficiently maintained,because the spacer 534 suppresses the lateral etching on the sidewall ofthe trench 519.

[0081] Again referring to FIG. 8, a description of a structure of acontact window of a semiconductor device fabricated by the method of thesecond embodiment of the present invention is presented.

[0082] A semiconductor substrate has an impurity active region 203. Alower dielectric layer 205 and an upper dielectric layer 209 are stackedon the semiconductor substrate 201 having the impurity active region203. The lower dielectric layer 205 comprises a first dielectric layer205 a and a second dielectric layer 205 b. The first dielectric layer205 a is a BPSG layer, an SOG layer or an O₃-TEOS layer. The seconddielectric layer 205 b and the upper dielectric layer 209 is a USGlayer, an HDP layer or an O₂-TEOS layer. The second dielectric layer 205b and the upper dielectric layer 209 have a lower wet etch rate thanetch rates of the first dielectric layer 205 a for an HF solution.

[0083] The impurity active region 203 is exposed to a contact window219′ which passes through the lower dielectric layer 205 and the upperdielectric layer 209.

[0084] The contact window 219′ comprises an upper contact window regionand a lower contact window region. The upper contact window regionpasses through the upper dielectric layer 209 and second dielectriclayer 205 b. The lower contact window region passes through the firstdielectric layer 205 a. As shown in the figure, a width 221′ of thelower contact window region is wider than a width of the upper contactwindow region. Meanwhile, conductive patterns 207 may intervene betweenthe upper dielectric layer 209 and the lower dielectric layer 205. Theconductive patterns 207 are spaced apart from the contact window 219′.That is, the upper contact window region passes through a region betweenthe neighboring conductive patterns 207, but does not expose theconductive patterns 207. Although the width of the upper contact windowregion is narrower than the space between the conductive patterns 207,an exposed surface of the impurity active region 203 can be wider thanthe space between the conductive patterns 207. That is, a width of abottommost region of the contact window can be controlled to be largerthan the space between the conductive patterns 207.

[0085] Moreover, although the wet etching is excessively performed, thesecond dielectric layer 205 b is prevented from exposing of theconductive patterns 207 because of the relatively low wet etch rate ofthe second dielectric layer 205 b. Therefore, it is possible to obtain areliable semiconductor device having high density.

[0086] Again referring to FIG. 10, a description of a structure of acontact window of a semiconductor device fabricated by the method of thethird embodiment of the present invention is presented.

[0087] In FIG. 10, a dielectric layer comprises a lower dielectric 305and an upper dielectric layer 309. A contact window 319′ passes throughthe dielectric layer and has a wider width 321′ of a lower region of thecontact window 319′ than a width of an upper region of the contactwindow 319′. The width 321′ of a lower region of the contact window 319′becomes wider as one approaches substrate 301. The lower dielectriclayer 305 is a TEOS layer, which has a wet etch rate for an HF solutionthat gradually decreases in a direction from the bottom to the top ofthe layer 305. The upper dielectric layer 309 has a thickness ofapproximately 4000 Å. It is more desirable that an upper region of theTEOS layer with 500-1000 Å thickness has the same etch rate as the etchrate of the upper dielectric layer 309. The upper dielectric layer 309is an USG layer, an HDP layer or an O₂-TEOS layer. The upper dielectriclayer 309 has a thickness of 4000 Å.

[0088] The upper dielectric layer 309 may be an HDP layer or an O₂-TEOSlayer.

[0089] A method for forming the TEOS layer having a changing etch rateis described in detail in U.S. Pat. No. 5,849,635 issued to Salman Akramet al. The desirable thickness of the lower dielectric layer 305 ispreferably within a range of 1000-6000 Å. In this embodiment, the lowerdielectric layer has a thickness of approximately 4000 Å. Though notdepicted in the drawings, a wiring material in the contact window 307contacts the substrate 301.

[0090] Conductive patterns 307 intervene between the upper dielectriclayer 309 and the lower dielectric layer 305. The conductive patterns307 can be made of polycrystalline silicon. One conductive pattern isisolated from the other conductive pattern with a predetermineddistance. A dielectric region with a selected width 320 intervenesbetween the contact window 319′ and the conductive patterns 307.

[0091] A width of a bottommost region of the contact window can be madelarger than the spacing between the conductive patterns 307. The contactwindow described above can increase the contact area and therebydecrease the contact resistance between the wiring layer and thesubstrate.

[0092] Again referring to FIG. 17, a description of a structure of acontact window of a semiconductor device fabricated by the method of thefifth embodiment of the present invention is presented.

[0093] In FIG. 17, a dielectric layer comprises a lower dielectric 505and an upper dielectric layer 509. A contact window 519′ passes throughthe dielectric layer and a capping layer 510 formed on the upperdielectric layer 509. The contact window 519′ has a width 521′ of alower region of the contact window 519′ greater than the width of anupper region of the contact window 519′. The lower dielectric layer 505and the upper dielectric layer 509 are formed using the same layer asdescribed in the third embodiment. The lower dielectric layer 505 andthe upper dielectric layer 509 may be formed using the same layer asdescribed in the first embodiment or the second embodiment. The cappinglayer 510 has a thickness of approximately 1000 Å and is made ofpolycrystalline silicon, silicon nitride or silicon oxynitride.

[0094] A spacer 534 is formed on the sidewall of an upper region of thecontact window 519′. The spacer 534 has a thickness of 300 Å and isformed of polycrystalline silicon, silicon nitride or siliconoxynitride. Though not shown in the drawings, a wiring material in thecontact window 507 having the spacer contacts the substrate 501.

[0095] Conductive patterns 507 are placed between the upper dielectriclayer 509 and the lower dielectric layer 505. The conductive patterns507 can be made of polycrystalline silicon. One of the conductivepatterns 509 is spaced apart from the other by a predetermined distance.A dielectric material with a selected width intervenes between thecontact window 519′ and the conductive patterns 507.

[0096] The spacer 534 insures electrical isolation between theconductive patterns 507 and the wiring layer.

[0097] In the fabrication method of the present invention, because thedry etching does not expose the substrate 501, damage to the impurityactive region can be prevented. An increased contact area can beobtained by controlling the etch rate of the lower dielectric layer 505a. Moreover, a high quality isolation characteristic between the wiringlayer and the conductive patterns 507 are obtained by using the polymerand the spacer 534.

[0098] In the drawings and specification, there have been disclosedtypical preferred embodiments of the invention and, although specificterms are employed, they are used in a generic and descriptive senseonly and not for purpose of limitation, the scope of the invention beingset forth in the following claims.

What is claimed is:
 1. A method of fabricating a semiconductor devicecomprising: forming a lower dielectric layer on a semiconductorsubstrate; forming an upper dielectric layer on the lower dielectriclayer; anisotropically etching the upper dielectric layer and the lowerdielectric layer to form a trench therein, the trench passing throughthe upper dielectric layer and having a depth less than a combinedthickness of the upper dielectric layer and the lower dielectric layer;and isotropically etching the lower dielectric layer exposed by thetrench to form a contact window, wherein a width of a lower region ofthe contact window is wider than a width of an upper region of thecontact window.
 2. The method of claim 1, wherein the anisotropicetching is performed using a dry etching process and the isotropicetching is performed using a wet etching process.
 3. The method of claim1, wherein the lower dielectric layer comprises a material layer havinga higher etch rate than the upper dielectric layer.
 4. The method ofclaim 3, wherein the lower dielectric layer comprises one selected fromthe group consisting of a BPSG layer, an SOG layer and an O₃-TEOS layerand the upper dielectric layer comprises one of selected from the groupconsisting of a USG layer, an HDP layer and O₂-TEOS layer.
 5. The methodof claim 1, wherein forming the lower dielectric layer comprises:forming a first dielectric layer on the semiconductor substrate; andforming a second dielectric layer on the first dielectric layer, whereinthe second dielectric layer has a lower etch rate than the firstdielectric layer during the isotropic etching.
 6. The method of claim 5,wherein the first dielectric layer comprises one selected from the groupconsisting of a BPSG layer, an SOG layer and an O₃-TEOS layer and thesecond dielectric layer comprises one selected from the group consistingof a USG layer, an HDP layer and an O₂-TEOS layer.
 7. The method ofclaim 1, wherein the etch rate of the lower dielectric layer increasesin a direction toward the substrate.
 8. The method of claim 7, whereinthe lower dielectric layer is formed by a process in which a flow rateof O₃ gas decreases and a flow rate of O₂ gas increases.
 9. The methodof claim 1, wherein the anisotropic etching comprises forming a polymerwith a thickness of 100-500 Å on a sidewall of the trench, and whereinthe polymer suppresses the isotropic etching.
 10. The method of claim 9,wherein the isotropic etching is performed by using a mixture includinga DI water, NH₄F and HF, wherein A volume percentage of the HF in themixture is approximately 0.1-0.4%.
 11. The method of claim 1 furthercomprises forming a spacer on a sidewall of the trench.
 12. The methodof claim 11 further comprises forming a capping layer on the upperdielectric layer.
 13. The method of claim 11, wherein the spacer is madeof a material selected from the group consisting of polycrystallinesilicon, silicon nitride and silicon oxynitride.
 14. The method of claim12, wherein the capping layer is made of a material selected from thegroup consisting of polycrystalline silicon, silicon nitride and siliconoxynitride.
 15. A method of fabricating a semiconductor devicecomprising: forming a first dielectric layer on a semiconductorsubstrate; forming a second dielectric layer on the first dielectriclayer, wherein the first dielectric layer comprises a material having ahigher isotropic etch rate than that of the second dielectric layer;anisotropically etching the first dielectric layer and the seconddielectric layer to form a trench, the trench passing through the seconddielectric layer; and isotropically etching the first dielectric layerto form a contact window such that a width of a lower region of thecontact window is wider than that of an upper region of the contactwindow.
 16. The method of claim 15, which further comprises forming aplurality of conductive patterns disposed between the second dielectriclayer and the upper dielectric layer.
 17. The method of claim 15,wherein the first dielectric layer is formed of one selected from thegroup consisting of a BPSG layer, an SOG layer and an O₃-TEOS layer andthe second dielectric layer is formed of one selected from the groupconsisting of an USG layer, an HDP oxide layer and an O₂-TEOS layer. 18.A method of fabricating a semiconductor device comprising: forming adielectric layer on a semiconductor substrate, wherein the dielectriclayer comprises a layer having an etch rate that increases in adirection toward the substrate; anisotropically etching a portion of thedielectric layer; and isotropically etching the dielectric layer to forma contact window.
 19. The method of claim 18, wherein the contact windowhas a width of a lower region of the contact window is wider than thatof an upper region of the contact window.
 20. The method of claim 18,wherein the layer is formed by a process in which a flow rate of O₃ gasdecreases and a flow rate of O₂ gas increases.
 21. A semiconductordevice comprising: a dielectric layer on a semiconductor substrate; acontact window passing through the dielectric layer; an upper region ofthe contact window having a sidewall substantially perpendicular to thesubstrate; and a lower region of the contact window having a width thatincreases in a direction toward the substrate.
 22. The semiconductordevice of claim 21 further comprises a plurality of conductive patternsdisposed between the second dielectric layer and the upper dielectriclayer, wherein the conductive patterns are spaced apart from the contactwindow.
 23. The semiconductor device of claim 22, wherein one of theplurality of conductive patterns is spaced apart from another one of theplurality of conductive patterns by a selected distance, and abottommost width of the contact window is wider than the selecteddistance.
 24. A semiconductor device comprising: a dielectric layer on asemiconductor substrate; a contact window passing through the dielectriclayer; an upper region of the contact window having a sidewallsubstantially perpendicular to the substrate; a lower region of thecontact window having a wider width than that of the upper region of thecontact window; and a spacer on the sidewall.
 25. The semiconductordevice of claim 24 further comprises a plurality of conductive patternsin the dielectric layer, wherein the plurality of conductive patterns isspaced apart from the contact window.
 26. The semiconductor device ofclaim 25, wherein one of the plurality of conductive patterns is spacedapart from another one of the plurality of conductive patterns with aselected distance, and a bottommost width of the contact window is widerthan the selected distance.
 27. The semiconductor device of claim 24further comprises a capping layer on the dielectric layer.
 28. Thesemiconductor device of claim 24, wherein the spacer is made of amaterial selected from the group consisting of polycrystalline silicon,silicon nitride and silicon oxynitride.
 29. The semiconductor device ofclaim 27, wherein the capping layer is made from a material selected ofthe group consisting of polycrystalline silicon, silicon nitride andsilicon oxynitride.
 30. A semiconductor device comprising: an interlayerdielectric layer on a semiconductor substrate, wherein the interlayerdielectric layer comprises a first dielectric layer, a second dielectriclayer and a upper dielectric layer; a contact window passing through theinterlayer dielectric layer, wherein a lower region of the contactwindow has a wider width than that of an upper region of the contactwindow; and a plurality of conductive patterns intervening between thesecond dielectric layer and the upper dielectric layer, wherein theconductive patterns are spaced apart from the contact window.
 31. Thesemiconductor device of claim 30, wherein one of the plurality ofconductive patterns is spaced apart from another one of the plurality ofconductive patterns with a selected distance, and a bottommost width ofthe contact window is wider than the distance.
 32. The semiconductordevice of claim 30, wherein a width of the contact window in the upperdielectric layer is substantially the same as a width of the contactwindow in the second dielectric layer.